The present invention relates to bipolar transistors and their fabrication, especially heterojunction bipolar transistors utilized in high-speed integrated circuits.
High performance circuits, especially those used for radio frequency chips, favor the use of heterojunction bipolar transistors (HBTs) to provide high maximum oscillation frequency fMAX and high transient frequency fT, also referred to as “cutoff frequency”. HBTs have a structure in which the base of the transistor includes a relatively thin layer of single-crystal semiconductor alloy material. As an example, an HBT fabricated on a substrate of single-crystal silicon can have a single-crystal base formed of silicon germanium (SiGe) having substantial germanium content and profile to improve high-speed performance. Such HBT is commonly referred to as a SIGe HBT.
A particularly advantageous type of HBT has a “graded base” in which the content of particular semiconductor materials varies according to depth within the base of the transistor. For example, in some graded base HBTs which have a base including SiGe, the germanium content varies continuously with depth across the thickness of the SiGe layer. In such “graded-base HBT, a significant quasi-electric field results during operation that decreases the transit time of charge carriers through the base. Decreased transit time, in turn, enables higher gain and cutoff frequency to be achieved than in transistors having the same semiconductor material throughout.
To increase the performance of an HBT, it is desirable to increase the transit frequency fT, and the maximum oscillation frequency fMAX. The transit frequency fT is the frequency at which the current gain of the transistor decreases to unity such that the HBT no longer amplifies currents above that frequency. FMAX is a function of fT and of parasitic resistances and parasitic capacitances (collectively referred to herein as “parasitics”) between elements of the transistor according to the formulafMAX=(fT/8ΠCcbRb)1/2.
The parasitics of the HBT include the following parasitic capacitances and resistances, as listed in Table 1:
TABLE 1Ccbcollector-base capacitanceCebemitter-base capacitanceRccollector resistanceReRemitter resistanceRbbase resistance
The parasitics having the most significant effect on performance are the collector-base capacitance Ccb and the base resistance Rb. The charging of the parasitic Ccb through the parasitic Rb has the greatest impact on power delivery that is reflected in the fMAX figure of merit. On the other hand, the emitter-base capacitance Ceb is the parasitic having the single largest capacitance. As explained more fully below, the value of Ceb indirectly but profoundly affects the value of Ccb, in that large Ceb requires high operational current. High operational current can require that the base have a high concentration of charge carriers. The ability of the device to sustain a high charge carrier concentration without the base dimension expanding during operation due to the well-known “base push-out effect” comes at the expense of increased Ccb. Thus, it is desirable to provide an HBT structure and method by which Ceb and Ccb are significantly reduced.
An example of a state of the art heterojunction bipolar-transistor (HBT) structure containing parasitics is illustrated in FIG. 1. As depicted in the cross-sectional view therein, an ideal or “intrinsic” device consists of a one-dimensional slice downward through the centerline 2 of the HBT, through emitter 4, intrinsic base layer 3, and collector 6. The emitter 4 is generally heavily doped with a particular dopant type, (e.g. n-type), and generally consists essentially of polycrystalline silicon (hereinafter, “polysilicon”). The intrinsic base 3 is predominantly doped with the opposite type dopant (e.g. p-type), and less heavily than the emitter 4. The collector 6 is doped predominantly with the same dopant (e.g. n-type) as the emitter 4, but even less heavily than the intrinsic base 3. Region 5 represents the depletion region disposed between the intrinsic base 3 and the collector 6, due to the p-n junction between the base and collector, which have different predominant dopant types. Region 7 represents the depletion region disposed between the intrinsic base 3 and the emitter 4, due to the p-n junction between the base and emitter, which have different predominant dopant types. Often, the intrinsic base 3 is formed of silicon germanium (SiGe), which is epitaxially grown on the surface of the underlying collector 6.
The ideal structure itself contains two capacitances that impact performance. There is the intrinsic emitter-base capacitance CBE,I at the junction 7 between the emitter 4 and the base 3. In addition, there is an intrinsic collector base capacitance CCB,I at the junction 5 between the collector and the base. These capacitances are related to the areas of the respective junctions, as well as to the quantities of dopant on either side of the respective junctions. Although these capacitances impact the power gain of the transistor, they are an inextricable part of the ideal transistor structure and thus cannot be fully eliminated. Since a one-dimensional transistor, free of all material beyond the intrinsic device, cannot be realized in a practical process, typically a transistor contains additional parasitics stemming from interaction between the intrinsic device and other material structures in which the intrinsic device is embedded, such structures helping to provide electrical access to and heat transfer from the intrinsic device. Among such additional parasitics is the extrinsic emitter base capacitance, shown in FIG. 1 as CBE,E 8. In higher performance transistors the dimension of the emitter in the lateral dimension is generally made smaller, in order to reduce the parasitic resistances. In such transistors, the region surrounding the emitter becomes larger for the same device area. As a result, the extrinsic portion of the emitter-base capacitance CEB,E increases as a proportion of the total emitter-base capacitance. Reductions in CEB,E, therefore, produce increasing benefits as the device dimensions decrease.
Through the well-known relation that transit time (˜1/fT) is proportional to (Ceb+Ccb)/IC (where IC is the collector current), and the observation that Ceb is generally significantly larger than Ccb, one can observe that fT and fMAX performance increase with decreasing Ceb. Alternatively, the reduction in Ceb is matched by a similar reduction in IC, resulting in the same performance at a lower power. With lower IC required for the needed performance, the collector doping can be reduced, which in turn causes the value of Ccb to fall, as a result. In such way, a reduction in Ceb will indirectly result in a decrease in Ccb and an increase in fMAX.
Therefore, it would be desirable to provide a structure and method of fabricating a bipolar transistor having reduced extrinsic emitter base capacitance CEB,E so as to achieve superior high-frequency current and power gain.
As provided by the prior art, differences exist among SiGe HBTs which allow them to achieve higher performance, or to be more easily fabricated. A cross-sectional view of one such prior art SiGe HBT 10 is illustrated in FIG. 2. Such non-self-aligned HBT 10 can be fabricated relatively easily, but other designs provide better performance. As depicted in FIG. 2, the HBT 10 includes an intrinsic base 12, which is disposed in vertical relation between the emitter 14 and the collector 16. The intrinsic base 12 includes a single-crystal layer of SiGe (a single-crystal of silicon germanium having a substantial proportion of germanium). The SiGe layer forms a heterojunction with the collector 16 and a relatively thin layer of single-crystal silicon 13 which is typically present in the space between the SiGe layer and the emitter 14.
A raised extrinsic base 18 is disposed over the intrinsic base 12 as an annular structure surrounding the emitter 14. The purpose of the raised extrinsic base 18 is to inject a base current into the intrinsic base 12. For good performance, the interface 24 between the raised extrinsic base 18 and the intrinsic base is close to the junction between the emitter 14 and the intrinsic base 12. By making this distance small, the resistance across the intrinsic base 12 between the interface 24 and the emitter 14 is decreased, thereby reducing the base resistance Rb (hence RC delay) of the HBT 10. It is desirable that the interface 24 to the raised extrinsic base be self-aligned to the edge of the emitter 14. Such self-alignment would exist if the raised extrinsic base were spaced from the emitter 14 only by the width of one or more dielectric spacers formed on a sidewall of the raised extrinsic base 18.
However, in the HBT 10 shown in FIG. 2, the interface 24 is not self-aligned to the emitter 14, and the distance separating them is not as small or as symmetric as desirable. A dielectric landing pad, portions 21, 22 of which are visible in the view of FIG. 2, is disposed as an annular structure surrounding the emitter 14. Portions 21, 22 of the landing pad separate the raised extrinsic base 18 from the intrinsic base 12 on different sides of the emitter 14, making the two structures not self-aligned. Moreover, as shown in FIG. 2, because of imperfect alignment between lithography steps used to define the edges of portions 21 and 22 and those used to define the emitter opening, the lengths of portions 21 and 22 can become non-symmetric about the emitter opening, causing performance to vary.
The landing pad functions as a sacrificial etch stop layer during fabrication. The formation of the landing pad and its use are as follows. After forming the SiGe layer of the intrinsic base 12 by epitaxial growth onto the underlying substrate 11, a layer of silicon 13 is formed over the SiGe layer 12. A layer of silicon dioxide is deposited as the landing pad and is then photolithographically patterned to expose the layer 13 of single-crystal silicon. This photolithographic patterning defines the locations of interface 24 at the edges of landing pad portions 21, 22, which will be disposed thereafter to the left and the right of the emitter 14. A layer of polysilicon is then deposited to a desired thickness, from which layer the extrinsic base 18 will be formed.
Thereafter, an opening is formed in the polysilicon by anisotropically etching the polysilicon layer (as by a reactive ion etch) selectively to silicon dioxide, such etch stopping on the landing pad. After forming a spacer in the opening, the landing pad is then wet etched within the opening to expose silicon layer 13 and SiGe layer 12. A problem of the non-self-aligned structure of HBT 10 is high base resistance Rb. Resistance is a function of the distance of a conductive path, divided by the cross-sectional area of the path. As the SiGe layer 12 is a relatively thin layer, significant resistance can be encountered by current traversing the distance from the extrinsic base under landing pad portions 21, 22 to the area of the intrinsic base 12 under the emitter 14, such resistance limiting the high speed performance of the transistor.
FIG. 3 is a cross-sectional view illustrating another HBT 50 according to the prior art. Like HBT 10, HBT 50 includes an intrinsic base 52 having a layer of silicon germanium and an extrinsic base 58 consisting of polysilicon in contact with the single-crystal intrinsic base 52. However, unlike HBT 10, HBT SO does not include landing pad portions 21, 22, but rather, the raised extrinsic base 58 is self-aligned to the emitter 54, the extrinsic base 58 being spaced from the emitter 54 by dielectric spacer. Self-aligned HBT structures such as HBT 50 have demonstrated high fT and fMAX as reported in Jagannathan, et al., “Self-aligned SiGe NPN Transistors with 285 GHz fMAX and 207 GHz fT in a Manufacturable Technology,” IEEE Electron Device letters 23, 258 (2002) and J. S. Rieh, et al., “SiGe HBTs with Cut-off Frequency of 350 GHz,” International Electron Device Meeting Technical Digest, 771 (2002). In such self-aligned HBT structures, the emitter 54 is self-aligned to the raised extrinsic base 58.
Several methods are provided by art which is background to the present invention for fabricating an HBT 50 such as that shown in FIG. 3. According to one approach, chemical mechanical polishing (CMP) is used to planarize the extrinsic base polysilicon over a pre-defined sacrificial emitter pedestal, as described in U.S. Pat. Nos. 5,128,271 and 6,346,453. A drawback of this method is that the extrinsic base layer thickness, hence the base resistance Rb, can vary significantly between small and large devices, as well as, between low and high density areas of devices due to dishing of the polysilicon during CMP.
In another approach, described in U.S. Pat. Nos. 5,494,836; 5,506,427; and 5,962,880, the intrinsic base is grown using selective epitaxy inside an emitter opening and under an overhanging polysilicon layer of the extrinsic base. In this approach, self-alignment of the emitter to the extrinsic base is achieved by the epitaxially grown material under the overhang. However, with this approach, special crystal growth techniques are required to ensure good, low-resistance contact between the intrinsic base and the extrinsic base.
As described in commonly assigned, co-pending U.S. patent application Ser. No. 09/962,738 of Freeman et al. filed Sep. 25, 2001, a self-aligned HBT is formed by a process including chemical mechanical polishing (CMP) steps. In such process, as shown in FIGS. 4A-4C, the intrinsic base 60 is formed by non-selective epitaxy over the collector 62. A raised extrinsic base 64 is formed by depositing polysilicon in an opening which has an upwardly projecting mandrel 66 in the center of the opening. Thereafter, as shown in FIG. 4B, the polysilicon is recessed by etching selectively to an exterior material of the mandrel, and a layer 68 of oxide is deposited in the opening. The oxide layer is then polished to the level of the mandrel and then the mandrel is thereafter removed, as shown in FIG. 4C. While the process described therein self-aligns the raised extrinsic base to the emitter, the base resistance Rb is dependent upon the accuracy and uniformity of recessing the polysilicon layer.
The article by M. W. Xu et al entitled “Ultra Low Power SiGe:C HBT for 0.18 μm RF-BiCMOS” published in Proceedings of the IEEE International Electron Devices Meeting, 2003 describes a method of optimizing the dimension of the emitter layer and its dopant profile in order to reduce the intrinsic portion of the emitter-base capacitance (CEB,I). However, the techniques proposed therein result in a larger space charge region between the emitter and the base of the transistor, which reduces peak performance.
Another technique for reducing the intrinsic portion of the emitter-base capacitance (CEB,I) is described in commonly owned, co-pending U.S. patent application Ser. No. 10/008,383 filed Dec. 6, 2001. According to such technique, as illustrated in FIGS. 5 and 6, the depth of the emitter 62 is intentionally varied, such that it has a lower depth D2 at the center of the transistor, while its depth D1 is greater at the perimeter. At high current injection the device perimeter dominates the transistor operation and the center is mostly parasitic. Under such conditions, this technique provides a more optimal structure for establishing a low CBE transistor.
It is desirable to provide a self-aligned HBT and method for making such HBT that reduces the extrinsic portion of the emitter-base capacitance (CEB,E), i.e., the capacitance outside of the operational portion of the transistor between the dielectric spacers 21, 22 (FIG. 2). Referring to illustrative FIG. 2, significant contributions to the CBE,E parasitic capacitance are provided where the emitter 14 is disposed in close proximity to the base 12 and 18 across a dielectric region or spacer. Additional parasitic capacitance results from the junction of the emitter layer with the base under and beyond the spacers 21, 22. There is opportunity for reducing the extrinsic emitter-base capacitance (CEB,E) and obtaining consequent performance enhancements. It would further be desirable to reduce the overall emitter-base capacitance without having to increase the thickness of the space charge region of the emitter and suffer loss of peak performance.
It would further be desirable to lower overall emitter-base capacitance, to permit the collector base capacitance to be lowered as a result.